With the increase in capacity of programmable devices such as FPGAs (Field Programmable Gate Array), the data size of configuration data is also increasing. Therefore, recently, it has become impossible to ignore the bit error rate of configuration data, which is bit stream data. Further, while the refinement of device processes has progressed to afford benefits in terms of power consumption, performance, cost, and the like, they are more susceptible to soft errors due to cosmic rays.
As a result, a phenomenon occurs in which the programmable device does not start normally even without a hardware fault. Consequently, every time the phenomenon occurs, a hardware repair must be performed, and an increase in the number of extra man-hours and costs is incurred. Furthermore, the programmable device becomes stuck if it does not start normally. This causes the system to go down, and causes inconvenience to the operating user. Therefore, a solution to these problems is also desired from a fail-safe perspective.
In volatile programmable devices such as FPGAs, techniques have been proposed that focus on the issue of rewriting circuit information (for example, see Patent Document 1 and Patent Document 2). In particular, the technique described in Patent Document 1 attempts to solve the above problems. In the technique described in Patent Document 1, when performing processing that reads circuit information into a FPGA and configures a logic circuit (hereinafter, also referred to as configuration processing), a redundant function is provided that prevents the FPGA from becoming stuck even if the configuration processing fails due to various factors.
The technique described in Patent Document 1, for example, is a configuration including a FPGA as shown in FIG. 10, and is a system that performs processing as shown in FIG. 11 and FIG. 12. In FIG. 10, the interface 201 is a config I/F. The interface 202 is an original I/F. Furthermore, reference symbol 203 denotes a signal line. In this system, when the FPGA 102 determines that a soft error has occurred in the circuit information read from the flash memory 100 via the PLD 101 (FIG. 11: step S3, True), the PLD 101 is notified of a configuration NG (FIG. 11: step S7). Causes of the soft error may, as described above, include abnormalities such as inversion of a bit in a bit stream (binary information consisting of 0s and 1s) included in the circuit information, and abnormalities caused by the effects of cosmic rays.
When the PLD 101 receives the notification of the configuration NG from the FPGA 102 (FIG. 12: step S22, True), it refers to the startup image information of the flash memory 100, and reads from the flash memory 100 other circuit information indicated by the inverted value of the value of the startup image information (FIG. 12: step S23). The PLD 101 transmits the read other circuit information to the FPGA 102 (FIG. 12: step S25). As a result, for example, in the case where two pieces of circuit information, circuit information A and circuit information B, exist as circuit information, and the configuration processing with circuit information A fails, it becomes possible for the configuration processing to be performed with circuit information B. If configuration processing with circuit information A fails but succeeds with circuit information B, a soft error is detected. On the other hand, when the configuration processing fails with both circuit information A and circuit information B, a hardware failure is detected.